SystemVerilog Language - Verification
Practical SystemVerilog: Enhance Your Skills for Modern Verification Techniques
Explore SystemVerilog’s capabilities to design powerful, reusable, and efficient testbenches. This course covers everything from the basics to advanced techniques, like assertions, randomization, and object-oriented programming, equipping you to create highly adaptable and organized verification environments. Each lesson is designed to introduce concepts through practical examples, empowering you to apply your skills to real-world verification workflows. By course end, you’ll have the expertise to manage complex data, optimize functional coverage, and build robust testbenches that simplify the verification process.
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Our course syllabus undergoes regular updates to reflect the latest advancements and best practices in the field. Students who purchase lifetime access to this course are entitled to receive these updates for free, ensuring they stay abreast of the most current content. Subscribers, on the other hand, can access the latest content for free as long as they maintain their subscription to the course. This approach guarantees that our students and subscribers always have access to the most relevant and up-to-date information in the field.
Created by EDA Academy
English
Last updated Oct 2024
SystemVerilog Language - Verification
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USD $99.9
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After this course you will be able to:
- Understand the scope, purpose, and features of SV
- Gain knowledge of SV’s basic verification features and techniques
- Organize verification code using SV’s clocking and verification blocks
- Generate and control random stimulus using SV randomization features
- Create and manage class-based test environments with SV OOP features
- Leverage polymorphism to promote testbench reusability and maintainability
- Generate effective stimulus data with SV’s class-based randomization
- Apply SV covergroup binning for enhanced functional coverage and analysis
- Utilize SV dynamic, associative arrays, and queues for data handling
This course includes:
- 9 Modules 35 Lectures
- 5.5 hours on-demand video
- 122 Quiz
- Certificate of completion
- Access on mobile and computer
- Ongoing support from EDA Academy
- Further learning plan
Course Content (Preview)
✓ Comprehensive Evolution of Verilog to SystemVerilog Standards
- Evolution of Verilog and SystemVerilog
- Original Verilog
- Verilog vs. VHDL Development
- Verilog-95 and Verilog-2001
- SystemVerilog extensions to Verilog
- SystemVerilog Replaces Verilog
✓ Data Type, Building Blocks, Features, and Interfaces in SystemVerilog
- Simplified and Synthesizable RTL Design
- Data Type Enhancements in SystemVerilog
- Key Building Blocks of SystemVerilog Verification
- Key Features of SystemVerilog Verification
- Simplifying Design with Interfaces
✓ Randomization, Functional Coverage, Assertions, and DPI in SystemVerilog
- Randomization in SystemVerilog
- Functional Coverage in SystemVerilog
- Assertions in SystemVerilog
- Direct Programming Interface in SystemVerilog
✓ String Operations
- SystemVerilog Strings Overview
- String Operators
- String Methods I
- String Methods II
✓ SystemVerilog Assertion Basics
- Immediate Assertions
- Action Blocks in Assertions
- Assertion Severity Levels
- Immediate Assertion for Simple Protocol Check
- Immediate vs Concurrent Assertions
✓ Fork-Join Behavior, and Process Control
- Enhancements to Fork-Join Behavior
- Process Control: disable fork, wait fork
✓ Event Scheduler, Program Block, and Final Blocks
- Verilog Event Scheduling
- SystemVerilog Event Scheduler
- SystemVerilog Program Block
- SystemVerilog Final Blocks
✓ Clocking Block Fundamentals
- Clocking Block
- Clocking Block Syntax
- Clocking Block Output Drive
- Clocking Block Input Sampling
✓ Clocking Block Skew
- Input and Output Skew in Clocking Blocks
- Example: Clocking Block with Skews
- Example: Output Skew Synchronization
✓ Multiple and Default Clocking Blocks, Cycle Delay, and Hierarchical Expressions
- Clocking Block Options and Defaults
- Cycle Delay in Clocking Blocks
- Using Hierarchical Expressions
✓ Structured Stimulus
- CPU Coverage Test Case
- CPU Test Stimulus Setup
- Looped CPU Instruction Stimulus
- Limitations of Structured Stimulus
✓ Random Stimulus
- Randomization and Constraints
- Pseudo-Random Number Generators
- Unsigned Random Number Functions
- Using randomize() for Scope Variables
✓ Random Stability, Random Seed, and Thread Seeding
- Ensuring Random Stability
- Setting the Random Seed
- Managing Thread Seeding
✓ Constraints, Random Weighted Case, and Random Sequence Generation
- Using Constraint Blocks
- Conditional Constraints
- Random Weighted Case: randcase
- Random Sequence Generation: randsequence
✓ Random Production
- Random Production Weights
- Production Statements: case, if-else, repeat
- Aborting Productions: break, return
- Passing Values in Productions
✓ Classes and Object-Oriented Concepts
- Class Overview in SystemVerilog
- Variables of the Class Type
- Class Handles and Memory Safety
- Class Properties and Methods
✓ Class Constructor and Class Example
- External Method Declaration
- Class Constructor
- Example: Class Definition and Instantiation
✓ Static Properties and Methods, and Class Composition
- Static Properties
- Static Methods
- Current Object Handle: this
- Class Properties as Class Instances
✓ Aggregation and Inheritance
- Aggregation vs. Inheritance
- Example: Simple Inheritance
- Example: Inheritance and Constructors
- Multi-Layer Inheritance
✓ Data Encapsulation and Class Parameters
- Data Encapsulation in Classes
- Class Parameters
✓ Polymorphism
- Polymorphism in SystemVerilog
- Copy a Sub-Class Instance to a Parent Handle
- Copy a Parent Instance to a Sub-Class Handle
- $cast
- Advantages of Polymorphism
- Accessing Class Members with Polymorphism
✓ Virtuality
- Virtual Method Resolution
- Class Method Resolution
- Virtual Classes and Pure Virtual Methods
✓ Randomization of Class Properties
- Random Class Properties
- Randomizing Class Objects: randomize()
- pre_randomize() and post_randomize()
- Randomization in Aggregate Classes
✓ In-Line Control, and Constraint Blocks
- In-Line Random Variable Control
- Controlling Randomization: rand_mode()
- Example: rand_mode()
- Constraint Blocks
- Constraint Block Inheritance
✓ Constraint Expressions
- Constraint Expressions: Set Membership
- Constraint Expressions: Weighted Distributions
- Constraint Expressions: Conditional Constraints
- Constraint Expressions: Iterative Constraints
✓ Controlling Constraints, Randomization Procedure, and Setting Seeds
- Controlling Constraints: constraint_mode()
- Example: Application of constraint_mode()
- Randomization Procedure
- Randomization Ordering and Solution Probability
- Setting the Random Seed: srandom()
✓ Functional Coverage
- Structural and Functional Coverage
- Types of Functional Coverage
- Data-Oriented Functional Coverage
- Defining a Coverage Model
✓ Automatic and User Defined Bins
- Automatic Coverage Bins
- Defining Explicit Bins
- Explicit Scalar and Vector Bins
- Example: Explicit Scalar and Vector Bins
- Counting Bins in a Covergroup
✓ Cross Products
- Cross Coverage
- Automatic Cross Bins Example
- Explicit Cross Bins and Selections
- Ignored and Illegal Cross Bins
- Defining Easier Cover Cross Bins
✓ Coverage Options
- Class-Based Coverage Model
- Tracking Transitions in Coverage
- Specify Coverage Options
- Reference: Type-Specific type_option Fields
- Reference: Instance-Specific option Fields
- Reference: Covergroup Methods
✓ Dynamic Arrays
- Dynamic Arrays
- Dynamic Array Example
✓ Associative Arrays
- Associative Arrays
- Associative Array Methods
- Example: Associative Array Lookup Table
- Example: Associative Array-More Efficient Lookup Table
✓ Queues
- Queues
- Queue Methods
- Example: Queue Methods
- Example: Queue Indexing
✓ Array Manipulation Methods
- Array Manipulation Methods
- Reference: Array Locator Methods
- Reference: Array Ordering Methods
- Reference: Array Reduction Methods
Requirements
To make the most of this course, you should have a background in digital design fundamentals, including some familiarity with Verilog and hardware design concepts. Basic experience in logic design and programming will help you quickly adapt to SystemVerilog’s advanced verification features. While this course will introduce SystemVerilog’s unique capabilities, prior knowledge of digital circuit testing concepts, such as assertions and testbenches, will provide a foundation for understanding how SystemVerilog enhances the verification process. The course is ideal for engineers or students ready to expand their skills in digital verification, particularly in creating efficient, reusable, and adaptable test environments. To get the most out of this course, it’s recommended that you meet the following prerequisites:
- Basic knowledge of digital design principles and logic gates.
- Understanding of logic design fundamentals, including combinational and sequential logic.
- Exposure to simulation processes and debugging tools.
- Familiarity with digital circuit testing strategies, including testbench basics.
- Knowledge of object-oriented programming concepts, especially for test environment structuring.
Who this course is for
- Engineers looking to master SystemVerilog for digital design
- Digital design students who want to learn SystemVerilog
- Hardware engineers transitioning from Verilog to SystemVerilog
- FPGA designers looking to enhance their design skills
- Verification engineers needing to use SystemVerilog in testbenches
- Designers looking to improve efficiency in RTL coding
- Professionals seeking to improve hardware design processes
- Engineers working with large digital systems
- Chip designers focusing on complex system design
- Embedded system developers using hardware description languages
Description
SystemVerilog is a powerful hardware description and verification language that has revolutionized digital design and verification. This course is designed to help you harness the language's full potential, whether you're new to SystemVerilog or looking to strengthen your skills. We’ll cover essential concepts like dynamic arrays, queues, classes, randomization, and coverage. You’ll gain hands-on experience with the latest techniques for generating, managing, and verifying test data, making this course ideal for engineers focused on efficient testbench creation and functional coverage. Whether you’re working on simplifying verification processes or aiming for robust, reusable testbench designs, this course provides a comprehensive and practical learning journey.
This course will guide you through the foundations and advanced applications of SystemVerilog, focusing on its verification capabilities. We begin with an overview of how SystemVerilog expands upon Verilog’s capabilities, introducing key concepts that enable better flexibility, simulation control, and testbench development. You’ll learn the differences between Verilog and SystemVerilog and explore critical features like assertions, randomization, and functional coverage.
As we progress, you’ll dive into practical topics like random stimulus generation, object-oriented programming for test environments, and class-based stimulus generation. Each module is designed to build your skills with real-world verification techniques, equipping you to handle complex data, apply dynamic testing strategies, and use SystemVerilog’s array and queue constructs. This hands-on approach ensures you’re ready to apply these concepts in any verification environment.
By the end of the course, you’ll have developed a solid understanding of how to apply SystemVerilog for efficient, reusable, and flexible testbench creation. You’ll also learn best practices in managing test data, coverage, and design verification, making you a valuable asset in modern digital verification workflows.
Learning Objectives
- You will explore the evolution of Verilog and how SystemVerilog has expanded on its capabilities. You will learn about the key differences between Verilog and SystemVerilog, including new data types, enhanced design flexibility, and advanced verification techniques. The course also covers how SystemVerilog introduces powerful tools for verification, such as assertions, randomization, and functional coverage, to simplify and improve the design process. You should be familiar with the extensions introduced by SystemVerilog, its added features for both designers and verification engineers, and how these tools can be integrated into your design flow.
- You’ll learn how to use SystemVerilog's string type, a dynamic, flexible way to handle and manipulate character data, making messages easier to create and manage. Time literals allow you to specify time delays with precision and clarity, improving readability and reliability in your code. Immediate assertions are covered to enable direct checks within your code, instantly identifying issues when specific conditions are met or failed. Enhancements to the fork…join construct will be explored, enabling more control over parallel tasks in verification setups. Additionally, you’ll review design features that have valuable applications in verification, including packages, structures, and arrays, making testbenches more adaptable and robust.
- Learn how to use SystemVerilog’s new verification blocks to improve the organization and effectiveness of your testbenches. Understand how the SystemVerilog event scheduler divides time slots into distinct regions, providing better control over simulation actions. Use programs to separate verification code from design, reducing the risk of race conditions and helping to organize code more clearly. Explore final blocks, which run at the conclusion of a simulation, enabling you to collect summary statistics and ensure all tasks are completed before simulation ends. Lastly, learn how clocking blocks help separate timing from functionality by managing signal sampling and driving, making testbench creation more straightforward and cycle delays easier to handle.
- Learn to use SystemVerilog’s randomization features to create both directed and random stimulus for verification. Understand how to apply pseudo-random number generators and seeding to control randomness, allowing you to generate large amounts of stimulus while still focusing on specific areas. Apply constraints to keep random values within legal limits and ensure meaningful test coverage for critical cases. Explore how randcase enables random selection of statements for execution, and how randsequence allows for the execution of a random sequence of statements, making stimulus generation efficient and adaptable for various testing scenarios.
- Learn how to use SystemVerilog’s Object-Oriented Programming (OOP) features to create classes that enhance the flexibility and structure of test environments. Gain skills in defining properties and methods for data manipulation, and in using constructors to initialize objects during simulation. Understand the benefits of encapsulation to protect data, as well as inheritance and polymorphism to create reusable, layered data types. These features allow you to dynamically create and destroy objects, making your testbench more versatile and maintainable. Additionally, explore how static properties and methods enable shared data access across instances, enhancing test efficiency and code organization.
- Learn to apply polymorphism and virtual methods in SystemVerilog to enhance testbench adaptability and modularity. Gain the ability to create virtual methods and virtual classes that allow base classes to be inherited and modified as needed, reducing the need to alter existing code. Understand how to cast and copy class instances, enabling flexible interaction between different class types. By using polymorphic behavior, you can make testbenches more reusable and easier to maintain, as well as customize them for various testing requirements without restructuring your code. These skills will help you build generic and extensible testbench frameworks.
- Learn to use randomization to control class properties, which enables generating complex and diverse test stimuli efficiently. Apply pre- and post-randomize methods to manage specific steps before and after randomization to produce tailored stimuli for different testing needs. Adjust constraints on properties to create valid and targeted data within defined boundaries. Switch easily between different constraint settings to control random generation based on test requirements. Understand how to set random seeds to reproduce results consistently, allowing repeatable testing scenarios. Through these skills, create more dynamic and comprehensive stimulus patterns that help cover corner cases and improve test coverage.
- Learn to implement data-oriented functional coverage using SystemVerilog covergroups, which enables defining what variables and events to sample. Set up coverage bins that count specific values and transitions, either automatically or explicitly. Use scalar and vector bins to monitor individual or combined value coverage, and define ignore_bins and illegal_bins to focus on valid cases. Understand cross-product coverage, including automatic and user-defined cross bins, to analyze interactions between different coverpoints. Gain control over the behavior of covergroups, coverpoints, and cross coverage, and use SystemVerilog functions to start, stop, and monitor coverage, and manage results for targeted verification.
- Learn to use SystemVerilog arrays—dynamic arrays, associative arrays, and queues—to handle and organize complex test data efficiently. Understand the versatility of dynamic arrays for managing data that changes size during simulation and the flexibility of associative arrays for sparse data sets, ideal for modeling extended address spaces. Apply queues for data that requires strict ordering, supporting both FIFO and LIFO mechanisms. Use array methods, including locator, ordering, and reduction, to enhance data access and manipulation. With these tools, manage large data sets effectively to improve simulation quality and test coverage.