SystemVerilog Language - Coverage
Achieving High Coverage in SystemVerilog for Reliable Verification
Gain a complete understanding of SystemVerilog coverage techniques in this course designed for verification engineers and digital design professionals. You’ll learn the essential types of coverage, from code and functional to data and control-oriented, with hands-on guidance on applying each one. Additionally, explore advanced methodologies such as Metric-Driven Verification (MDV) and Assertion-Based Verification (ABV) to enhance the thoroughness and precision of your verification processes. By the end, you'll have practical tools to confidently measure, optimize, and improve your coverage results, ensuring high-quality and reliable hardware design.
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Our course syllabus undergoes regular updates to reflect the latest advancements and best practices in the field. Students who purchase lifetime access to this course are entitled to receive these updates for free, ensuring they stay abreast of the most current content. Subscribers, on the other hand, can access the latest content for free as long as they maintain their subscription to the course. This approach guarantees that our students and subscribers always have access to the most relevant and up-to-date information in the field.
Created by EDA Academy
English
Last updated Nov 2024
SystemVerilog Language - Coverage
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USD $149.9
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$89.9
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After this course you will be able to:
- Determine and apply key coverage types in project design
- Apply block, expression, toggle, and FSM coverage to source code
- Implement Data-Oriented Coverage models for functional verification
- Construct Control-Oriented Coverage using SystemVerilog Assertions
- Integrate functional coverage into metric driven verification
- Enhance verification completeness using coverage metrics
- Analyze and utilize MDV methodology for improved verification
- Adopt Assertion-Based Verification into verification methodology
- Identify verification tools that are available for Assertion-Based Verification
This course includes:
- 9 Modules 29 Lectures
- 5.9 hours on-demand video
- 104 Quiz
- Certificate of completion
- Access on mobile and computer
- Ongoing support from EDA Academy
- Further learning plan
Course Content (Preview)
✓ Coverage fundamentals
- Coverage Goals
- Types of Coverage
- Code Coverage Essentials
- Functional Coverage for Data Signals
- Functional Coverage for Control Signals
- FSM (Finite State Machine) Coverage
- Transaction Coverage
✓ Coverage basic process
- The Coverage Process
- Step 1: Instrument the Design
- Step 2: Collect the Coverage Data
- Step 3: Reduce the Coverage Data
- Coverage Collection & Reduction Overview
- Step 4: Analyze the Coverage Data
- Comprehensive Coverage Methods
✓ Block Coverage
- Block Coverage Basics
- Code Block Definition
- Rules for Code Blocks
- How Many Code Blocks
✓ Branch, Expression, and Toggle Coverage
- Understanding Code Branches
- Understanding Expression Coverage
- Understanding Toggle Coverage
- Default Toggle Coverage Constructs
✓ FSM Coverage
- Understanding FSM Coverage
- Guidelines for FSM Extraction
- Accepted FSM Coding Guidelines
- One-Block FSM Coding Example
- Two-Block FSM Coding Example
- One-Hot FSM Coding Example
✓ Covergroup Definition and Instantiation
- Data-Oriented Functional Coverage Overview
- Defining a Covergroup
- Instantiating a Covergroup
✓ Coverpoint Bins
- Defining Coverpoints
- Automatically Created Coverpoint Bins
- Defining Coverpoint Value Bins
- Example Defining Coverpoint Value Bins
- Defining Coverpoint Transition Bins
- Example Defining Coverpoint Transition Bins
✓ Coverpoints and Cover Crosses
- Defining Coverpoint Crosses
- Automatically Created Cross Bins
- Defining Cross Bins
- Example Defining Cross Bins
✓ Covergroups in Classes
- Using Covergroups in Classes
- Example Using Covergroups in Classes
✓ Verification directives, and Action blocks
- Control-Oriented Functional Coverage Overview
- Key Verification Terms and Definitions
- Directing Functional Verification Tools
- Specifying Action Blocks in Assertions
✓ Boolean
- Composing Boolean Expressions
- Boolean Functions
✓ Sequence
- Composing Sequence Expressions
- Clocking Sequences
- Sequence Fusion and Concatenation
- Defining Cycle Delay Ranges
- Defining Sequence Operations
- Defining Sequence Repetition: Consecutive
- Defining Sequence Repetition: Non-Consecutive
- Defining Sequence Repetition: Go-To
- Declaring and Instantiating Sequences
- Using Local Variables in Sequences
- Overview of SVA Sequence Operators
- Example SVA Sequences
✓ Property
- Composing Property Expressions
- Weak and Strong Properties
- Declaring and Instantiating Properties
- Overview of SVA Property Operators
- Example SVA Properties
✓ Metric-Driven Verification: Process, Benefits, and Flow
- Metric-Driven Verification Review
- Metric-Driven Verification Flow
- Benefits of Metric-Driven Verification
✓ Comprehensive Coverage: Strategies and Techniques
- Key Coverage Considerations
- Coverage Options Overview
- Metric-Driven Verification Goals
- Integrating Coverage Techniques
- Explicit Coverage in SystemVerilog
- Coverage Placement Strategies
✓ Interface Monitor, and Module Monitor Coverage
- Interface Monitor Coverage Declaration
- Interface Monitor Coverage Trigger
- Module Monitor Coverage
- When to Cover
- Comparing With and Without MDV
✓ Granularity, Manual effort, and Effectiveness
- Key Verification Metrics
- Understanding Verification Granularity
- Optimizing Manual Verification Effort
- Enhancing Verification Effectiveness
✓ Completeness, Verification environment reusability, and Simulation result reusability
- Achieving Verification Completeness
- Verification Environment Reusability
- Simulation Result Reusability
✓ Transaction-Driven Verification, Constrained random generation, and Automatic result checking
- Coverage-Driven Verification Overview
- Transaction-Driven Verification
- Constrained Random Generation
- Automatic Result Checking
✓ Coverage collection, Directed tests, and Stages of CDV
- Coverage Collection
- Directed Tests
- Stages of Coverage-Driven Verification
✓ MDV Concepts and Productivity
- Metric Driven Verification (MDV) Overview
- MDV: A Closed-Loop Process
- MDV: Enhancing Productivity
- MDV Productivity Benefits
✓ Directed Testing vs. CDV
- Bug Detection Analysis: Test-Driven vs. Metric-Driven
- Tool-Reported Coverage vs. Plan-Based Coverage
- Limitations of Directed Testing
- Benefits of Coverage-Driven Verification
- Importance of Planning in CDV
✓ MDV methodology, and Benefits of MDV
- MDV Across Verification Platforms
- Metric-Driven Verification with Verification Manager
- Key Advantages of Metric-Driven Verification
✓ Traditional Verification and Assertion Based Verification
- Traditional Verification
- Traditional Verification Disadvantages
- Assertion-Based Solution
- Advantages of Assertion-Based Verification
✓ Verification Testbench based on Assertion
- Before Assertion-Base Verification
- After Assertion-Base Verification
- Verification Testbench based on Assertion
✓ Assertion Based Verification Methodology
- Property specification in Assertion-Based Verification
- Assertion in Simulation Testbench
- Assertion in Formal Verification Testbench
- Assertion-Based Verification Methodology
✓ Assertion Based Verification Flow
- Coverage Driven Verification
- Who Writes Assertions and Why
- Introduction to Assertion-Based Verification
- Assertion-Based Verification Flow
✓ ABV in Formal, Simulation, Emulation, and Functional Coverage
- Assertion-Based Verification (ABV) in Formal
- Assertion-Based Verification (ABV) in Simulation
- Assertion-Based Verification (ABV) in Emulation/Acceleration
- Assertion-Based Verification (ABV) in Functional Coverage
✓ ABV in Plan to Closure Methodology
- Dynamic & Formal Verification
- Formal Verification Technology Factors
- Simulator Overhead for Dynamic ABV
- ABV in Plan to Closure Methodology
Requirements
This course is designed for individuals with a foundational knowledge of digital design and a working familiarity with SystemVerilog who are looking to advance their skills in verification. An understanding of testbenches, basic verification principles, and an interest in learning about coverage techniques will be essential to grasp the course content. Familiarity with coverage metrics and some hands-on experience in digital design verification will enable participants to gain the most from this course. Participants should have access to a SystemVerilog simulation environment, as practical application and testing of coverage techniques will be a significant component of the learning experience. To get the most out of this course, it’s recommended that you meet the following prerequisites:
- Prior experience with digital logic design and development.
- Understanding of logic design fundamentals, including combinational and sequential logic.
- Familiarity with digital circuit testing strategies, including testbench basics.
- Familiarity with basic SystemVerilog syntax and programming structure.
- Interest in exploring advanced verification methodologies.
Who this course is for
- Engineers looking to master SystemVerilog for digital design
- FPGA designers looking to enhance their design skills
- Verification engineers needing to use SystemVerilog in testbenches
- Engineers working on complex digital system verification
- Practitioners interested in automated test methodologies
- Embedded system developers using hardware description languages
- Testbench developers looking to refine their coverage models
- Verification engineers seeking deeper coverage skills
- Digital designers who want to optimize testing accuracy
- Engineers interested in Metric-Driven Verification (MDV)
Description
This course offers a comprehensive approach to mastering coverage in SystemVerilog for hardware verification. Designed to help engineers assess verification completeness, it covers key coverage types like code, functional, data-oriented, and control-oriented coverage. You’ll gain practical insights into using each type to gauge the thoroughness of your test environment. By focusing on Metric-Driven Verification (MDV) and Assertion-Based Verification (ABV), the course provides a structured methodology for improving verification quality and efficiency. Whether you're a beginner looking to build foundational skills or an experienced verification engineer aiming to optimize your process, this course equips you with the knowledge and practical tools to address real-world verification challenges effectively.
This course is designed to provide you with a comprehensive understanding of coverage techniques essential in hardware verification. Coverage plays a crucial role in verifying that designs are tested thoroughly, focusing on areas like code coverage, data-oriented functional coverage, and control-oriented coverage. Through practical examples, you’ll see how to instrument designs for coverage and gather coverage data that measures the quality of your testbench.
Additionally, the course introduces Metric-Driven Verification (MDV), a methodology that uses metrics to guide and enhance verification efficiency. MDV helps streamline the verification process, highlighting gaps in testing and reducing unnecessary simulations. You’ll learn how to apply MDV principles to make your verification process more efficient and focused, ultimately achieving higher productivity and better coverage results.
The course also covers Assertion-Based Verification (ABV), teaching you how assertions enhance verification across simulation, formal verification, and emulation. ABV provides a strong framework for detecting design issues, and you'll gain hands-on experience in specifying assertions that support the verification process from start to finish. By the end of this course, you’ll be well-equipped to apply advanced SystemVerilog coverage methods in your verification projects.
Learning Objectives
- Identify how coverage fits into your design flow. Understand coverage fundamentals, including setting clear goals and selecting the types of coverage that will help you meet these objectives. Develop the ability to apply different types of coverage, such as code, toggle, FSM, functional, and transaction coverage, to measure the testbench’s verification completeness. Gain the skills to use coverage data to highlight areas that require focused verification efforts and estimate the remaining verification workload. Learn to instrument the design for coverage collection, gather and organize coverage data, and analyze the results to determine additional testing needs.
- Identify the design source code that requires code coverage. Determine the specific areas of the design that should undergo code coverage based on the project’s verification needs. Learn to apply different types of code coverage, such as block coverage, expression coverage, toggle coverage, and FSM coverage, to assess the thoroughness of the design verification. Gain insight into each coverage type’s role and the appropriate contexts for their application. Develop the ability to use these coverage metrics to strengthen the verification of the design source.
- Define a data coverage model tailored to the requirements of the verification project. Distinguish between code coverage and functional coverage, emphasizing the role of data-oriented functional coverage. Learn the usage of SystemVerilog covergroups to create flexible data coverage models. Explore the concepts of covergroup definition, instantiation, coverpoints, and cover crosses. Gain proficiency in utilizing covergroups within classes, enabling a structured approach to data-oriented functional verification. These skills will support creating a robust data coverage model that captures key verification metrics.
- Define the control coverage model for the verification project by using SystemVerilog Assertions (SVA). Distinguish between code coverage and functional coverage, focusing on control-oriented functional coverage. Understand key components such as functional verification directives, action blocks, and various expressions including Boolean, sequence, and property expressions. Use these components to create SystemVerilog assertions that capture control-oriented coverage, enabling an accurate assessment of control behaviors in the design.
- Understand how metric-driven verification (MDV) improves verification efficiency by focusing on coverage metrics and reducing unnecessary tests. Learn to apply MDV methodology to monitor coverage in a UVC interface and track the accuracy of the module scoreboard. Use MDV to replace time-consuming test writing with strategic constraint sets that ensure verification completeness while minimizing redundant simulations. By tracking coverage metrics, identify gaps in verification and determine which additional tests are necessary, achieving a clear understanding of verification “doneness” and improving overall test quality.
- Develop an understanding of key verification metrics, such as granularity, manual effort, effectiveness, and completeness, to evaluate and enhance verification quality. Explore the role of verification environment reusability, simulation result reusability, and coverage-driven verification as methods to improve efficiency in functional verification. Understand the benefits of transaction-driven and constrained random stimulus generation, as well as automatic result checking and coverage collection, in a coverage-driven approach. Learn to compare verification methodologies using these metrics to determine the best-suited method for specific project goals.
- Recognize the key concepts of Metric Driven Verification (MDV) and apply the MDV methodology effectively. Gain an understanding of the closed-loop nature of MDV and explore its benefits, including productivity enhancements, better test planning, and improved bug detection. Recognize the importance of tool-reported and plan-based coverage, as well as the limitations of directed testing. Understand how MDV helps to streamline verification efforts across different platforms and how it provides a systematic approach to achieve comprehensive coverage and verification goals.
- Assertion-based verification (ABV) is a verification approach where the user specifies design properties in SVA/PSL language and considers assertions as a primary means of verification at each verification stage, while also combining various verification techniques and gradually adopting ABV in the verification flow. This course explores the different verification stages and the verification breakthroughs driven by assertion verification techniques.
- The ABV methodology can be applied to formal, simulation, and acceleration verification. Each verification technique corresponds to different verification tools. Based on the advantages and disadvantages of each verification technique, use assertions reasonably and effectively. Many verification environment indicators can be collected in the verification flow. The assertion results reported in formal, simulation, and acceleration verification can be collected together to maximize the achievement of verification metrics.
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