Identify how coverage fits into your design flow. Understand coverage fundamentals, including setting clear goals and selecting the types of coverage that will help you meet these objectives. Develop the ability to apply different types of coverage, such as code, toggle, FSM, functional, and transaction coverage, to measure the testbench’s verification completeness. Gain the skills to use coverage data to highlight areas that require focused verification efforts and estimate the remaining verification workload. Learn to instrument the design for coverage collection, gather and organize coverage data, and analyze the results to determine additional testing needs.

Identify the design source code that requires code coverage. Determine the specific areas of the design that should undergo code coverage based on the project’s verification needs. Learn to apply different types of code coverage, such as block coverage, expression coverage, toggle coverage, and FSM coverage, to assess the thoroughness of the design verification. Gain insight into each coverage type’s role and the appropriate contexts for their application. Develop the ability to use these coverage metrics to strengthen the verification of the design source.

Define a data coverage model tailored to the requirements of the verification project. Distinguish between code coverage and functional coverage, emphasizing the role of data-oriented functional coverage. Learn the usage of SystemVerilog covergroups to create flexible data coverage models. Explore the concepts of covergroup definition, instantiation, coverpoints, and cover crosses. Gain proficiency in utilizing covergroups within classes, enabling a structured approach to data-oriented functional verification. These skills will support creating a robust data coverage model that captures key verification metrics.

Define the control coverage model for the verification project by using SystemVerilog Assertions (SVA). Distinguish between code coverage and functional coverage, focusing on control-oriented functional coverage. Understand key components such as functional verification directives, action blocks, and various expressions including Boolean, sequence, and property expressions. Use these components to create SystemVerilog assertions that capture control-oriented coverage, enabling an accurate assessment of control behaviors in the design.

Understand how metric-driven verification (MDV) improves verification efficiency by focusing on coverage metrics and reducing unnecessary tests. Learn to apply MDV methodology to monitor coverage in a UVC interface and track the accuracy of the module scoreboard. Use MDV to replace time-consuming test writing with strategic constraint sets that ensure verification completeness while minimizing redundant simulations. By tracking coverage metrics, identify gaps in verification and determine which additional tests are necessary, achieving a clear understanding of verification “doneness” and improving overall test quality.

Develop an understanding of key verification metrics, such as granularity, manual effort, effectiveness, and completeness, to evaluate and enhance verification quality. Explore the role of verification environment reusability, simulation result reusability, and coverage-driven verification as methods to improve efficiency in functional verification. Understand the benefits of transaction-driven and constrained random stimulus generation, as well as automatic result checking and coverage collection, in a coverage-driven approach. Learn to compare verification methodologies using these metrics to determine the best-suited method for specific project goals.

Recognize the key concepts of Metric Driven Verification (MDV) and apply the MDV methodology effectively. Gain an understanding of the closed-loop nature of MDV and explore its benefits, including productivity enhancements, better test planning, and improved bug detection. Recognize the importance of tool-reported and plan-based coverage, as well as the limitations of directed testing. Understand how MDV helps to streamline verification efforts across different platforms and how it provides a systematic approach to achieve comprehensive coverage and verification goals.

Assertion-based verification (ABV) is a verification approach where the user specifies design properties in SVA/PSL language and considers assertions as a primary means of verification at each verification stage, while also combining various verification techniques and gradually adopting ABV in the verification flow. This course explores the different verification stages and the verification breakthroughs driven by assertion verification techniques.

The ABV methodology can be applied to formal, simulation, and acceleration verification. Each verification technique corresponds to different verification tools. Based on the advantages and disadvantages of each verification technique, use assertions reasonably and effectively. Many verification environment indicators can be collected in the verification flow. The assertion results reported in formal, simulation, and acceleration verification can be collected together to maximize the achievement of verification metrics.