This course is designed for engineers, students, and professionals who aim to master SystemVerilog Assertions (SVA) and elevate their verification capabilities. Whether you are new to SVA or looking to deepen your existing knowledge, this course will equip you with the skills to write effective assertions and apply them to real-world projects. To get the most out of this course, it’s recommended that you meet the following prerequisites:

Assertions are embedded pieces of code that act like observers. They can be inserted anywhere in the design code. When used in a verification environment, assertions help to identify design bugs earlier and more easily. This method is a highly efficient way to improve work productivity. Through assertions, we can capture specific design behaviors and gain detailed knowledge of how the design should operate. Assertions are crucial for increasing the observability and controllability of a design. Assertions are a language for describing design behavior. Their syntax is fundamental, requiring systematic learning to use assertion-based verification techniques effectively.

Assertion-based verification provides an effective way to improve verification quality by offering better controllability and observability of design bugs. Using assertions ensures that interface designs are executed correctly. They help discover deep design bugs, identify hard-to-find corner cases. We can also analyze and improve test cases in simulation through coverage environments with assertions.

Our course focuses on the basic syntax of the SystemVerilog Assertions (SVA) language, which is part of the SystemVerilog language defined in the IEEE 1800 industry standard. We cover key terminology, the four verification directives (assert, assume, cover, and restrict), and the four structural levels (Boolean expressions, sequences, properties, and assertions). We also discuss the basics of immediate and concurrent assertions.

The course provides a detailed look at simple Boolean expressions, sequences, sequence operations, coverage, and reusable properties in SVA. Through analyzing and studying specific cases, we summarize methods for writing concise and efficient property codes. This course will guide you on how to apply assertion-based verification techniques in real projects, making it an essential skill for starting practical projects.

Leverage assertions and translate design specifications into assertions. Assertions are written by various people at various times during the development of a product, from conception through design and implementation, and during verification. Assertions can be written at different levels of abstraction, in various hardware design language contexts. Assertions take some effort to write. At the same time, they can make design verification much more efficient, can simplify debugging, and can significantly improve overall productivity.

SVA is part of the SystemVerilog language, defined in the industry standard IEEE1800 for SystemVerilog. SVA is a property description language with basic syntax composed of four levels: Boolean expressions, sequences, properties, and verification directives.

Boolean expressions are the foundation of the SVA language. They are the first level of the SVA structure, and all design behavior descriptions start with them. This course explains and demonstrates simple assertions based on Boolean expressions.

Sequences are the second level of the SVA structure. Cycle-based properties are usually described using sequences. A sequence contains multiple Boolean expressions separated by ##N, where N is the number of cycles between expressions. This course explains sequences and shows assertions based on them.

Sequences include a wide range of powerful operators and functions that allow the construction of complex sequences. SVA has many complex operators to build sequences, and using advanced sequence combination operators and features makes defining sequences and properties easier.

Besides verifying functional correctness, it is essential to check the completeness of the verification process. Monitoring and managing verification progress, and evaluating the quality of verification through completeness results, is crucial. Coverage can be introduced to analyze the effectiveness of test cases and observe the efficiency of test vectors.

Liveness assertions and fairness assumptions do not have meaning in simulation; they are only effective in formal verification. A liveness assertion means that something good will eventually happen, while a fairness assumption means an input must eventually be false. These concepts are related to the IEEE standards of the SVA language. Note that the same property can behave differently under different syntax standards.