This advanced PSL course is designed for verification engineers and professionals with a solid understanding of digital design and basic verification methodologies. To fully benefit from the course, you should be familiar with fundamental concepts of Assertion-Based Verification (ABV), as well as having experience with simulation and formal verification tools. To get the most out of this course, it’s recommended that you meet the following prerequisites:

The application of assertion techniques and the related languages have been continuously updated and developed. As assertion languages are designed to express complex behaviors, the ongoing development of assertion techniques allows us to better utilize assertions as an important verification method. PSL provides many structures and operators that are not commonly used. These powerful structures can describe complex sequences. However, not all property structures or operators are useful. It is important to compare the advantages and disadvantages of these new structures or operators with traditional sequence descriptions to decide whether to use them.

Assertion Based Verification provides an effective way to improve quality of verification by providing better controllability and observability of design errors. ABV is enabled with specification of assertions in the design. Assertions are executable specification of the design and are mostly written as 'assert' properties used to check the design functionality and 'cover' properties primarily used for functional coverage. Assertion can be verified using different ABV technologies: Formal, Simulation and Emulation/Acceleration.

Our course mainly focuses on advanced uses of the Property Specification Language (PSL). Here, we cover the following topics: First, the basic concepts of assertion-based verification (ABV) and a systematic ABV methodology. Second, how to use the powerful PSL syntax to describe complex assertion sequences through practical examples. Third, an overview of the basic principles of ABV and how to build ABV units using a standardized approach. Fourth, demonstrations of PSL's practical applications through specific real-world cases, including how to write assertions and properties. Fifth, analyzing issues of functional verification completeness and setting realistic expectations for the role of EDA tools throughout the verification process.

Assertion-based verification (ABV) is a verification approach where the user specifies design properties in SVA/PSL language and considers assertions as a primary means of verification at each verification stage, while also combining various verification techniques and gradually adopting ABV in the verification flow. This course explores the different verification stages and the verification breakthroughs driven by assertion verification techniques.

The ABV methodology can be applied to formal, simulation, and acceleration verification. Each verification technique corresponds to different verification tools. Based on the advantages and disadvantages of each verification technique, use assertions reasonably and effectively. Many verification environment indicators can be collected in the verification flow. The assertion results reported in formal, simulation, and acceleration verification can be collected together to maximize the achievement of verification metrics.

We can some powerful constructs for describing complex assertion sequences. ended(), Convert the completion of a sequence into a Boolean. Allow multiple concurrent sequences to be described. Can be parameterized. Parameterized sequences and properties. Allow use of common sequence definitions on different signals. Parameters can even be sequences or properties. % Macros, forall construct and for used in declarations. Replication of a property or sequence over, for example, all individual elements of a bus. Local variables and procedural blocks. Multi-clocked properties.

Demonstrate issues which affect when a property should be evaluated. Clocking properties not straight forward. Need to consider delta cycle issues, just like with RTL. There are many ways to evaluate properties safely. Designers responsibility to understand the issues.

Understand capabilities of Verification Units. Check your tool documentation for support of VUnit’s. Gives some degree of PSL HDL flavor independence. Allow more structured, reusable and flexible approach to verification.

Provide sufficient knowledge on specific designs and protocols to enable lab exercises to be completed. PSL provides an efficient and powerful way to verify designs. The approach to writing properties needs some thought and should be included in the test plan. A "divide and conquer" methodology works well. Plan the structure of your assertions and identify key branch conditions. Declare alternative behaviors and key conditions as sequences. Build compound sequences using conjunction, disjunction, repetition etc. Define enabling conditions and triggers. Use coverage to check assertions are triggered. Remember PSL does not remove the obligation to write a thorough testbench.

Functional Verification is about risk management not verifying everything We need to minimize the chances of a critical bug escaping the verification process There are many tools and methodologies to help us do this We cannot abdicate the responsibility for thorough verification to automation Automation only helps with manging data, predictable repetitive task and computing Functional Verification is still a human process vulnerable to human error There is no single verification methodology which worst best for every circumstance all of the time.