Instructor: Peng Yu
Greetings, I am Peng Yu, an industry veteran with close to two decades of experience in the semiconductor and VLSI sectors, focusing on digital circuit design and verification, as well as EDA tool application and design fields. For 14 years, I contributed to Cadence, a leading EDA vendor, specializing in providing technical support for formal verification.
Currently, I serve as a senior staff technical consultant in formal verification at a startup, where my role encompasses a wide array of responsibilities. These include the development of formal verification IP, creation of online courses on platforms like eda-academy.com, consultation on formal verification technical matters, provision of customized training for individuals and businesses, and delivery of professional formal verification outsourcing services for companies.
With my extensive background and expertise, I am dedicated to sharing my knowledge and insights with learners at EDA Academy, empowering them to excel in the field of formal verification.
Experiences
Formal Signoff for Various Designs
With a wealth of experience in formal verification projects, I specialize in two critical solutions: formal signoff with full proof and formal signoff with coverage. Throughout my career, I have successfully tackled a diverse range of designs, including Instruction units, Standard interfaces, User-defined interfaces, Bus matrices, Caches, MMUs, Schedulers, DMA controllers, Memory controllers, Interrupt controllers, Power management units, and various specific functional modules.
Development of Unique Formal Methodology
Drawing on this extensive project experience and a deep understanding of various design types, I have developed a unique formal verification methodology. This methodology has been honed through practical application and has proven highly effective in ensuring design correctness and efficiency.
Development of Formal Verification IP Library
One of my key achievements has been the independent creation of a comprehensive formal verification IP library. This library comprises nearly 200 units, encompassing basic, common, VIP, and flow libraries. These resources, combined with my methodology, have been successfully deployed in the product development workflows of numerous leading chip companies. The results speak for themselves, with significant improvements in verification effectiveness and performance observed across the board.
Instructor Offering Diverse Formal Training
Experienced in formal verification projects, providing comprehensive formal solutions for key components of leading companies in the IC industry, and guiding and promoting project completion. Also experienced as an instructor, offering small, medium, and large-scale training and workshops to engineers from various companies.
Courses
Formal Verification Training Course series offered by EDA Academy, instructed by Peng Yu, covers a comprehensive range of topics in formal verification, providing a thorough understanding of key technical points and fundamental concepts essential for success in the field of IC verification.
In this course, you will master all the key technical points of formal verification. You will learn about the principles, methodologies, and applications of formal verification, laying a solid foundation for more advanced topics covered in subsequent courses.
Formal Verification Fundamentals
Explore essential inquiries in this course, delving into basic concepts in the world of formal verification. Gain insights into the underlying principles of formal verification and understand its benefits and limitations.
Take your first step into formal verification project practice with SystemVerilog Assertions (SVA) coding. Learn the fundamentals of SVA coding and its application in formal verification projects.
Similarly, this course introduces Property Specification Language (PSL) coding for formal verification. Learn how to write PSL properties and use them effectively in formal verification projects.
Property Checking
Building robust formal testbenches is crucial for effective formal verification. In this course, you will learn strategies for effective property checking, ensuring thorough verification of your designs.
Functional Signoff with Formal
Master functional signoff techniques using formal verification in this course. Gain a comprehensive understanding of functional signoff and learn how to achieve exhaustive verification.
Formal Verification Applications
Unlock the versatility of formal verification in solving complex design problems. This course explores various applications of formal verification, demonstrating its effectiveness in real-world scenarios.
Formal Verification: Auto Formal
Automate your verification process with level one formal verification techniques for efficient structural checks. This course focuses on automating formal verification to enhance productivity and accuracy.
Formal Verification: Formal Apps
In this course, uncover structured excellence in formal verification with level two formal verification applications. Learn advanced techniques for comprehensive verification.
Formal Verification: Unit Signoff
Go beyond the basics with level three unit-level formal signoff techniques. This course equips you with the skills to verify complex unit designs effectively.
Formal Verification: Block Signoff
Achieve formal expertise in block-level signoff with this course. Master level four formal signoff methodologies for comprehensive verification of block-level designs.
Formal Verification: System Signoff
Gain a deep dive into system-level formal verification with this course. Learn level five formal verification techniques for verifying complex system designs with confidence.
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